package ChiselStudy

import chisel3._
import chisel3.util._

class Shift extends Module {
  val io = IO(new Bundle {
//    val a = Input(SInt(8.W))
//    val b = Input(UInt(8.W))
    val c = Output(UInt(8.W))
  })

//  val op1 = Wire(SInt(8.W))
//  op1 := "b01".U.asSInt

  val op1 = Wire(UInt(4.W))
  op1 := "b1110".U

  val op2 = Wire(UInt(2.W))
  op2 := 1.U

//  io.c := (op1.asSInt >> op2).asUInt
  io.c := op1.asSInt << op2

}

object Shift_Gen extends App {
  println("Generating the adder hardware")
  (new chisel3.stage.ChiselStage).emitVerilog(new Shift(),Array("--target-dir", "generated/ChiselStudy/Shift"))
}
